In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. Analyze design and propose best compression technique. Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus.In depth knowledge and hands on experience in MBIST insertion and Memory test validation. Expertise in Mentor tools is plus. Hands on experience on JTAG boundary scan (IEEE ., . ) is plus. Work with IDDQ constrains, validation, and pattern generation. Owns STA constraints and work with STA team to resolve timing violations Experience in RTL and Gate level simulations of scan and MBIST test vectors. Expertise in scripting languages such as perl, shell, etc.Ability to work with global teams.Ability to learn and adapt to new tools and methodologies.Ability to do multitasking & work on several high priority designs in parallel.Excellent problem solving skillsExcellent communication and team work skills
Sankalp Placement India P. Ltd is looking for Any Graduate candidates only.
Key Skill: Engineering / R&D Company Description Long known for the consistent delivery of quality personnel, Sankalp is a nationally recognized organization that has been headquartered in Mumbai, India fulfilling organizational staffing requirements.. Sankalp is known for its Executive Search and Headhunting Skills, delivers the superlative HR Solutions. Being focused on quality, our forte has been our TAT (turn around time) which is most essential.
Looking for Any Graduate graduates profile.